The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for manufacturing a high voltage MOS transistor switching device. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
A high voltage MOS device is an example of an integrated circuit chip that often requires smaller designs but should achieve higher voltage capability. Smaller designs often cause lower voltages, which are undesirable for these types of integrated circuit devices. Higher breakdown voltages are desired but are often at the expense of size, which limits the number of integrated circuits that can be fabricated on a single wafer. High voltage MOS transistors operable at more than 30 volts must often use Lateral Drain MOS device structures, commonly called LDMOS, for higher junction breakdown voltages. Unfortunately, LDMOS structures are often larger in size. Smaller high voltage MOS transistors rely upon Drain Diffusion MOS device structures (DDMOS). Although these DDMOS structures are smaller, they are generally operable at voltages from about 12 volts to 20 volts. These and other limitations will be described in further detail throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.